中国电子技术网
设为齐乐娱乐老虎机官网 网站地图 加入收藏
 
  1. MCU|FPGA|嵌入式|模拟设计|RF|电源管理|传感器|测试测量|LED|DSP|存储器|AC/DC转换器|DC/DC转换器|放大器|铁电存储|
  1. 智能可穿戴|齐乐娱乐老虎机官网|自动化与马达控制|人工智能|智能能源|智能电源|VR/无人机|智能手机|智能照明|智能医疗|5G技术|智能汽车
  1. 齐乐娱乐老虎机官网 >  解决方案 >  [齐乐娱乐老虎机官网] Lattice iCE40 UltraPlus系列移动开发平台(MDP)解决方案

[齐乐娱乐老虎机官网] Lattice iCE40 UltraPlus系列移动开发平台(MDP)解决方案

关键词:FPGA 智能手机 平板电脑 手持设备 iCE40 UltraPlus系列 时间:2019-06-05 11:05:53       来源:齐乐娱乐老虎机官网

lattice公司的iCE40 UltraPlus系列是超低功耗FPGA和传感器管理器,设计用于超低功耗移动应用如智能手机,平板电脑和手持设备.iCE40 UltraPlus系列和iCE40 Ultra系列产品兼容,包含了除了大电流IR LED驱动器外的所有iCE40 Ultra系列功能;此外,它还增加1Mb SRAM, DSP区块,以及LUT,支持移动设备中的常开语音识别功能而不需要更大功耗的语音编译码器(CODEC).iCE40 UltraPlus系列还集成了SPI和I2C区块,以便和所有移动传感器和应用处理器接口,还有两个支持I3C器件接口的I/O引脚.此外,还有两个片上振荡器10kHz和48MHz,LFOSC (10 kHz)非常适合于低功耗的常开应用,而HFOSC (48 MHz)则用来叫醒功能.它的DSP功能区块可以卸载应用处理器来预处理移动设备来的信息如语音数据.RGB PWM IP具有三个24mA恒流RGB输出,可提供直接驱动LED所必须的逻辑电路,而不需外接MOSFET或缓冲器.iCE40 UltraPlus系列有两个器件型号,2800到5280查找表(LUT),有多达120kb 区块RAM以及1024kb单端口SRAM,能和用户逻辑工作.采用先进的40nm低功耗工艺制造,待机功耗低到100 μA.主要用在常开语音识别应用,智能手机,平板电脑和消费类手持设备,手持通信和工业设备,多传感器管理应用,传感器预处理和融合以及常开传感器应用与USB 3.1 Type C电缆检测/供电应用.本文介绍了iCE40 UltraPlus系列主要特性,iCE40UP5K架构图, PLB框图,sysDSP功能框图,sysDSP 8位x8位乘法器框图,DSP 16位x16位乘法器框图以及移动开发平台iCE40 UltraPlus MDP板主要特性,电路图和材料清单.

iCE40UltraPlus™ family from Lattice Semiconductor is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. iCE40UltraPlus is compatible with Lattice’s iCE40 Ultra family devices, containing all the functions iCE40 Ultra family has except the high current IR LED driver. In addition, the iCE40 UltraPlus features an additional 1 Mb SRAM, additional DSP blocks, with additional LUTs, all which can be used to support an always-on Voice Recognition function in the mobile devices, without the need to keep the higher power consuming voice codec on all the time.

The iCE40 UltraPlus family includes integrated SPI and I2C blocks to interface with virtually all mobile sensors and application processors. In addition, the iCE40 UltraPlus family also features two I/O pins that can support the interface to I3C devices. There are two on-chip oscillators, 10 kHz and 48 MHz, the LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities.

The iCE40 UltraPlus family also features DSP functional block to off-load Application Processor to pre-process information sent from the mobile device, such as voice data. The RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 UltraPlus provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer.

The iCE40 UltraPlus family of devices are targeting for mobile applications to perform all the functions in iCE40 Ultra devices, such as Service LED, GPIO Expander, SDIO Level Shift, and other custom functions. In addition, the iCE40 UltraPlus family devices are also targeting for Voice Recognition application.

The iCE40 UltraPlus family features two device densities, 2800 to 5280 Look Up Tables (LUTs) of logic with programmable I/Os that can be used as either SPI/I2C interface ports or general purpose I/O’s. Two of the iCE40 UltraPlus I/Os can be used to interface to higher performance I3C. It also has up to 120 kb of Block RAMs, plus 1024 kb of Single Port SRAMs to work with user logic.

The iCE40 UltraPlus family of ultra-low power FPGAs has three devices with densities ranging from 2800 to 5280 Look-Up Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programmable logic, these devices also feature Embedded Block RAM (EBR), Single Port RAM (SPRAM), on-chip Oscillators (LFOSC, HFOSC), two hardened I2C Controllers, two hardened SPI Controllers, PWM IP, three 24 mA RGB LED open-drain drivers, I3C interface pins, and DSP blocks. These features allow the devices to be used in low-cost, high-volume consumer and mobile applications.

The iCE40 UltraPlus FPGAs are available in very small form factor packages, as small as 2.11 mm × 2.54 mm. The small form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 2.1 lists the LUT densities, package and I/O pin count.

The iCE40 UltraPlus devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per pin” basis. In addition, the iCE40 UltraPlus devices offer two I/Os with dynamic control on the pull-up resistors to support I3C interface.

The RGB PWM IP in the iCE40 UltraPlus devices provides controls for driving the 24 mA LED Sink driver, including color controls, LED ON/OFF time, and breathe rate.

The iCE40 UltraPlus devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 UltraPlus family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 UltraPlus. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 UltraPlus device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 UltraPlus FPGA family. Lattice also can provide fully verified bitstream for some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding Lattice’s reference designs or fully-verified bitstreams, contact your local Lattice representative.

iCE40 UltraPlus系列主要特性:

 Flexible Logic Architecture
 Two devices with 2800 to 5280 LUTs
 Offered in WLCS and QFN packages
 Ultra-low Power Devices
 Advanced 40 nm low power process
 As low as 100 μA standby current typical
 Embedded Memory
 Up to 1024 kb Single Port SRAM
 Up to 120 kb sysMEM™ Embedded Block RAM
 Two Hardened I2C Interfaces
 Two I/O pins to support I3C interface
 Two Hardened SPI Interfaces
 Two On-Chip Oscillators
 Low Frequency Oscillator – 10 kHz
 High Frequency Oscillator – 48 MHz
 24 mA Current Drive RGB LED Outputs
 Three drive outputs in each device
 User selectable sink current up to 24 mA
 On-chip DSP
 Signed and unsigned 8-bit or 16-bit functions
 Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC)
 Flexible On-Chip Clocking
 Eight low skew global signal resource, six can be directly driven from external pins
 One PLL with dynamic interface per device
 Flexible Device Configuration
 SRAM is configured through:
 Standard SPI Interface
 Internal Nonvolatile Configuration Memory (NVCM)
 Ultra-Small Form Factor
 As small as 2.11 mm × 2.54 mm

iCE40 UltraPlus系列应用:

 Always-On Voice Recognition Application
 Smartphones
 Tablets and Consumer Handheld Devices
 Handheld Commercial and Industrial Devices
 Multi Sensor Management Applications
 Sensor Pre-processing and Sensor Fusion
 Always-On Sensor Applications
 USB 3.1 Type C Cable Detect / Power Delivery Applications

图1. iCE40UP5K架构图(顶视图)

图2. iCE40UP5K PLB框图

图3.sysDSP功能框图(16位x16位乘法-累加)

图4.sysDSP 8位x8位乘法器框图

图5.DSP 16位x16位乘法器框图

图6. I/O组和可编I/O单元框图

移动开发平台iCE40 UltraPlus MDP

Thank you for choosing the Lattice iCE40 UltraPlus™ Mobile Development Platform (MDP) Board.
This MDP board is an easy-to-use platform for demonstrating various features of the iCE40 UltraPlus for mobile applications. The MDP form-factor is similar to a mobile device (cell phone), with various sensors, display,Bluetooth communication, and others. The board contains four individual iCE40 UltraPlus devices, each configured with a unique set of interfaces to support multiple demonstrations.

移动开发平台iCE40 UltraPlus MDP板主要特性:

Features that can be demonstrated using this board include:
 Mobile Display (Onboard 1.54 inch 240 x 240 RGB wearable type display with MIPI DSI interface)
 Camera (Onboard VGA 640 x 480 sensor with CSI and parallel video interface option)
 Image and facial recognition
 Microphones (Onboard Dual I2S and Dual PDM microphones with audio amp, 3.5 mm and expansion connectors)
 Voice recognition
 Audio beam forming capabilities
 Sensors (Various Mobile Type Sensors with expansion connector)
 RGB LED
 Pressure Sensor
 Compass Sensor
 Gyroscope Sensor
 Accelerometer Sensor

移动开发平台iCE40 UltraPlus MDP主要特性:

The iCE40 UltraPlus Mobile Development Platform development kit includes the items below.
 iCE40UltraPlus Mobile Development Platform– PCB, case, and integrated Li-ion battery featuring:
 Four iCE40 UltraPlus devices (U1-U4 iCE40UP5K-UWG30) in 30-Ball WLCSP packages
 Large capacity of onboard SPI Flash memory (U37 Micron M25P80 8Mb) to store the FPGA demo bitstream for all four iCE40 UltraPlus devices
 Example of a PCB design using 0.40 mm Ball Pitch package
 Control switches to select which of the four devices is active (only one device is active at a time)
 Standard USB cable for device programming (Lattice part number HW-USBN-2A, HW-USBN-2B or equivalent)
 RoHS-compliant packaging and process
 Key Components
 iCE40UP5K-UWG30 (4 pieces)
 Power Regulation
 Bluetooth module
 MIPI LCD Mobile Display (1.54 inch 240 x 240 RGB LH154Q01)
Camera image sensor OVM7692 VGA 640 x 480 (CSI and parallel video interface option)
 Microphones (Dual I2S and Dual PDM microphones with audio amp, connectors for 3.5 mm and expansion)
 RGB LED
 Sensors that include:
– Barometric pressure sensor
– Compass sensor
– 3D accelerometer and 3D gyroscope sensor
– Three-axis linear accelerometer sensor
 Pre-loaded Demo – The kit includes a pre-loaded MIPI LCD Mobile Display demo.
 USB Connector Cable – A mini-B USB port provides power, a programming interface and communication channel for a PC to communicate directly to iCE40 devices.

图7.移动开发平台iCE40 UltraPlus MDP板外形图(顶视)

图8.移动开发平台iCE40 UltraPlus MDP板外形图(底视)

图9.移动开发平台iCE40 UltraPlus MDP板电路图(框图)

图10.移动开发平台iCE40 UltraPlus MDP板电路图:iCE40UP5K FPGA A-显示器


图11.移动开发平台iCE40 UltraPlus MDP板电路图:iCE40UP5K FPGA B-音频

图10.iCE40 UltraPlus MDP板电路图:iCE40UP5K FPGA C-传感器


图11.iCE40 UltraPlus MDP板电路图:iCE40UP5K FPGA D-照相机

图12.iCE40 UltraPlus MDP板电路图:共同元件-SPI

图13.iCE40 UltraPlus MDP板电路图:显示器电路

图14.iCE40 UltraPlus MDP板电路图:音频电路

图15.iCE40 UltraPlus MDP板电路图:传感器和RGB电路

图16.iCE40 UltraPlus MDP板电路图:照相机电路

图17.iCE40 UltraPlus MDP板电路图:USB编程

图18.iCE40 UltraPlus MDP板电路图:电源

图19.iCE40 UltraPlus MDP板电路图:共同元件

图20.iCE40 UltraPlus MDP板电路图:电池连接器和充电器
移动开发平台iCE40 UltraPlus MDP板材料清单:







详情请见:
http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus
http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusMobileDevPlatform
FPGA-DS-02008-1-6-iCE40-UltraPlus-Family-Data-Sheet.pdf
FPGA-EB-02007-1-2-iCE40-UltraPlus-Mobile-Development-Platform.pdf
Schematics iCE40 Ultra Plus Mobile Development Platform MDP.pdf

  1. 分享到:
 
猜你喜欢
  1. 验证码: 点击换一张
  2. 注册|忘记密码?
齐乐娱乐老虎机官网 中国电子行业研发工程师一站式服务平台 关于齐乐娱乐老虎机官网| 广告招商| 联系我们| 招聘信息| 友情链接| 齐乐娱乐老虎机官网导航| 手机齐乐娱乐老虎机官网 |   齐乐娱乐老虎机官网官方微博 Copyright © 2000- 齐乐娱乐老虎机官网 版权所有      京ICP备19016262号-2      增值电信业务经营许可证粤B2-20050142      公安机关备案号44030402002188 Tel: 010-62985649, 0755-33322333     Fax: 0755-33322099
齐乐娱乐老虎机